// Copyright (C) 1953-2022 NUDT
// Verilog module name - local_count 
// Version: V4.1.0.20221206
// Created:
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module local_count
    (
        i_clk,
        i_rst_n,
        
		i_local_cnt_rst,
        ov_local_cnt        
    );

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n;
input                   i_local_cnt_rst;
// output
output  reg [23:0]      ov_local_cnt;
// internal reg&wire for inport fifo
always@(posedge i_clk or negedge i_rst_n)
    if(!i_rst_n) begin
        ov_local_cnt       <= 24'b0;
    end
    else begin
        if(i_local_cnt_rst)begin
            ov_local_cnt       <= 24'd24;//i_local_cnt_rst跨时钟域需要2拍
        end
        else begin
            ov_local_cnt       <= ov_local_cnt + 24'd8;
        end
    end

endmodule